My TTL Processor

This is my newest project that I started in early September 2009. I wanted to know how a cpu works on the gate level so, I decided to build one myself! I used Donn's TTL Computer Processor project to help me understand the concepts. For more details about the computer and my progress, visit my blog page. It is not built yet but my design has been sucessfully simulated. Updated December 2009.

Here are the current specs:

Estimated speed is around 4Mhz
200+ 74xx, 74LS, and 74F series TTL chips. Everything is wire wrapped on three main boards (shown below) and one separate display board. The display board shows the contents of the registers and the control bus from the microcode roms. Estimated power usage will be between 3-4 amps at 5 volts.
7 general purpose registers. 6 of which can be used as (3) register pairs for 16-bit operations.
Stack Pointer which allows CALLs, RETurns, and Interrupts to be used.
Indirect addressing by using register pair HL.
Vectored Interrupts with 7 prioritized inputs.
16-bit ALU capable of adding, subtracting, BCD correction circuit for decimal addition or subtraction, ones and twos compliment, Boolean operations, shift left or right.
Flag register contains Zero, Half Carry, Carry, Overflow, Minus, and Interrupt Enable.
8-bit Data Bus and 16-bit Address Bus which supports up to 64Kb of memory. Supports up to 256 unique instructions.
Most instructions take between 5-7 states.
Supports up to 32 states per instruction.
Basically has similar features of the Z80 but is less complex (instruction wise).
The finite state machine is microcode based and consists of (5) 128k flash roms.
The microcode will be written using the AS Macroassembler.
The first basic “operating system” will just consist of a small program that will receive data from the PC via the serial port and place it into ram. Then a jump is made to the beginning of ram.

Currently implemented instructions:

Note: All instructions have been tested in the simulator.

ADD
SUB
ADDC (Add with carry)
SUBC (Subtract with carry)
AND (Boolean AND operation)
OR (Boolean OR operation)
XOR (Boolean XOR operation)
TC (Two’s compliment. Invert all bits and add 1)
NOT (Invert all bits. One’s compliment)
LD (Load data into/out of register. Transfer data from one register to another. Also used for indirect addressing)
CP (Compare)
CALL (Call a subroutine. PC is pushed onto the stack)
RET (Return from subroutine. Top of stack is popped into the PC)
RETI (Return from interrupt service routine. Clear interrupt bit and the top of stack is popped into the PC)
JP (Jump to a location in memory)
HALT (Stop executing instructions)
NOP (No operation)
PUSH (push register onto stack)
POP (take top of stack and save to register)
IN (Receive byte from I/O port into register)
OUT (Output byte to specified I/O port from register)
RLA (Shift and Rotate)
RLCA
SLA
SRL
DJNZ (Decrement register B and jump to address until B=0)
LDIR (Transfers data from one location to another. More details below)

I've sucessfully simulated my TTL processor design! Here's a screenshot of the display page (there are actually 10 pages total). In the screenshot it is running at 10Hz but it can be simulated up to 500Hz (or until it takes too much cpu on my desktop). It's running an instruction equivalent to the LDIR instruction for the Z80. Here's a quote from the Z80 manual which explains the instruction's function: "This 2-byte instruction transfers a byte of data from the memory location addressed by the contents of the HL register pair to the memory location addressed by the DE register pair. Both these register pairs are incremented and the BC (Byte Counter) register pair is decremented. If decrementing causes the BC to go to zero, the instruction is terminated. If BC is not zero, the program counter is decremented by two and the instruction is repeated." This instruction takes 23 states to fully execute. I've also written (microprogrammed) other instructions to test the processor's function: ADD,SUB, Boolian operations, LD, JP Z, Rotate/Shift, PUSH, POP, and a few others. So far, its been successful. I mainly just need to test the CALL, RET, and Interrupts to fully test the processor.

UPDATE Dec 09:

The Interrupt system and the Call and Return instructions all work correctly now. All implemeted instructions function correctly. I'm calling the design complete and it's ready to be built (see my latest blog entry for more info)!

Here is a diagram of the data path of the processor. It shows the data flow between the different elements.

IR = Instruction Register (16-Bit)
PC = Program Counter Register (16-Bit)
SP = Stack Pointer Register (16-Bit)
A-L = General Purpose Registers (8-Bit)
TMP A, B, 16 = Temporary Registers (not user accessible)
TRI = Tri-state buffers
ALU = Arithmetic Logic Unit

Here are the wire wrap boards that i'm going to use:

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Last Updated December 2009

Contact: Tai Oliphant